TMPR4937 datasheet(481/552 Pages) TOSHIBA

481 / 552 page

Chapter 15 Interrupt Controller

15-35

Bit

Mnemonic

Field Name

Explanation

Read/Write

IS22

Interrupt Status 22 IRINTREQ [22] status

This bit indicates the PCIERR error status.

1: Interrupt requests

0: No interrupt requests

IS21

Interrupt Status 21 IRINTREQ [21] status

This bit indicates the NDFMC interrupt status.

1: Interrupt requests

0: No interrupt requests

⎯

Reserved

⎯

IS19

Interrupt Status 19 IRINTREQ [19] status

This bit indicates the TMR [2] interrupt status.

1: Interrupt requests

0: No interrupt requests

IS18

Interrupt Status 18 IRINTREQ [18] status

This bit indicates the TMR [1] interrupt status.

1: Interrupt requests

0: No interrupt requests

IS17

Interrupt Status 17 IRINTREQ [17] status

This bit indicates the TMR[0] interrupt status

1: Interrupt requests

0: No interrupt requests

IS16

Interrupt Status 16 IRINTREQ [16] status

This bit indicates the PCIC interrupt status

1: Interrupt requests

0: No interrupt requests

IS15

Interrupt Status 15 IRINTREQ [15] status

This bit indicates the PDMAC interrupt status.

1: Interrupt requests

0: No interrupt requests

IS14

Interrupt Status 14 IRINTREQ [14] status

This bit indicates the IRC interrupt status

1: Interrupt requests

0: No interrupt requests

IS13

Interrupt Status 13 IRINTREQ [13] status

This bit indicates the DMA [3] interrupt status

1: Interrupt requests

0: No interrupt requests

IS12

Interrupt Status 12 IRINTREQ [12] status

This bit indicates the status of DMA [2] interrupts.

1: Interrupt requests

0: No interrupt requests

IS11

Interrupt Status 11 IRINTREQ [11] status

This bit indicates the status of DMA [1] interrupts.

1: Interrupt requests

0: No interrupts requests

IS10

Interrupt Status 10 IRINTREQ [10] status

This bit indicates the status of DMA [0] interrupts.

1: Interrupt requests

0: No interrupt requests

Figure 15.4.14 Interrupt Source Status Register (2/3)

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