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TMPR4937 Datasheet(PDF) 486 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 486 Page - Toshiba Semiconductor |
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486 / 552 page ![]() Chapter 15 Interrupt Controller 15-40 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 31 16 Reserved : Type : Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R/W : Type 0x0000 : Default Bit Mnemonic Field Name Explanation Read/Write 31:16 ⎯ ⎯ Reserved ⎯ 15:0 PF1 [15:0] Flag 1 Interrupt Request Flag 1 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 0 also since they are the same registers. Writes to Flag Register 1 operate as follows: Write Write from the TX49/H3 core 1: Set the flag bit 0: No change Write from other devices (DMAC, PCIC) 1: Clear the flag bit 0: No change Read: Read the flag bit R/W Figure 15.4.17 Interrupt Request Flag Register 1 |
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