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TMPR4937 Datasheet(PDF) 514 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 514 Page - Toshiba Semiconductor |
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514 / 552 page ![]() Chapter 21 Electrical Characteristics 21-8 21.5.4 External Bus Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Symbol Condition Min. Max. Unit SYSCLK Cycle Time tCYC_SYSCLK Buffer fixed: CL=50 pF, 8 mA 7.5 ⎯ ns SYSCLK High Time tHIGH_SYSCLK Buffer fixed: CL=50 pF, 8 mA 4 ⎯ ns SYSCLK Low Time tLOW_SYSCLK Buffer fixed: CL=50 pF, 8 mA 4 ⎯ ns ADDR[19:5] Output Delay tVAL_ADDR2 For CL=150 pF, 16 mA buffer 1.5 6.5 ns CE[7:0]* Output Delay tVAL_CE Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns OE* Output Delay tVAL_OE Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns SWE* Output Delay tVAL_SWE Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns BWE[3:0]* Output Delay tVAL_BWE Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns ACE Output Delay tVAL_ACE Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns BUSSPRT* Output Delay tVAL_DQM Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns DATA[63:0] Output Delay (H →L, L→H) tVAL_BUS For CL=50 pF, 16 mA buffer 1.5 6.5 *1) ns DATA[31:0] Output Delay (Hi-Z →Valid) tVAL_DATA2ZV For CL=50 pF, 16 mA buffer 1.5 8.5 ns DATA[31:0] Ouput Delay (Valid →Hi-Z) tVAL_DATA2VZ For CL=50 pF, 16 mA buffer 1.5 8.5 ns DATA[31:0] Input Setup Time tSU_DATA2 6.0 ⎯ ns DATA[31:0] Input Hold Time tHO_DATA2 0.5 ⎯ ns ACK* Output Delay (H →L, L→H) tVAL_ACK Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns ACK* Output Delay (Hi-Z →Valid) tVAL_ACKZV Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns ACK* Output Delay (Valid →Hi-Z) tVAL_ACKVZ Buffer fixed: CL=50 pF, 8 mA 1.5 8.5 ns ACK* Input Setup Time tSU_ACK 6.0 ⎯ ns ACK* Input Hold Time tHO_ACK 0.5 ⎯ ns *1) When the speed of the External Bus is set to 1/3 speed, the delay becomes the GBUSCLK cycle + 6.5 ns. EBCCRn.SP of the External Bus Controller sets the speed of the External Bus. Figure 21.5.5 Timing Diagram: External Bus Interface tSU_* tHO_* outputs valid inputs valid tVAL_* SYSCLK OUTPUT INPUT tCYC_SYSCLK tHIGH_SYSCL tLOW_SYSCL |
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