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TMPR4937 Datasheet(PDF) 511 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 511 Page - Toshiba Semiconductor

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Chapter 21 Electrical Characteristics
21-5
21.5 AC characteristics
21.5.1 MASTERCLK AC characteristics
(Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Max.
Unit
Boot configuration
ADDR[2]=H
7.5
80
ns
MASTERCLK Cycle
tMCP
Boot configuration
ADDR[2]=L
30
320
ns
Boot configuration
ADDR[2]=H
12.5
133.3
MHz
MASTERCLK Frequency *1)
fMCK
Boot Configuration
ADDR[2]=L
3.125
33.3
MHz
MASTERCLK High Time
tMCH
2
⎯
ns
MASTERCLK Low Time
tMCL
2
⎯
ns
TMPR4937XBG-300
50
300
CPUCLK Frequency
fCPU
TMPR4937XBG-333
50
333
MHz
MASTERCLK Rise Time
tMCR
⎯
1.5
ns
MASTERCLK Fall Time
tMCF
⎯
1.5
ns
*1) TX4937 operation is only guaranteed when the power is stable, PLL secures the PLL oscillation
stability time tMCP_PLL and is in the Enable state.
Figure 21.5.1 Timing Diagram: MASTERCLK
21.5.2 Power on AC characteristics
(Tc = 0 – 70
°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Max.
Unit
PLL Oscillation Stability Time
tMCP_PLL
10
ms
CGRESET* Width Time
fMCK_PLL
1
ms
RESET* Width Time
tMCH_PLL
1
⎯
ms
*1) VCCInt and VCCIO must start up sumultaneously, or VCCInt must be first.
The difference of the stand up time ota power supply within 100 m seconds.
Figure 21.5.2 Timing Diagram: Power On Reset
tMCH
tMCL
tMCP
MASTERCLK
0.8 VCC
0.2 VCC
tMCR
tMCF
tMCP_PLL
tMCK_PLL
MASTERCLK Oscillation Stability Time
tMCH_PLL
VCCInt, VCCIO
*1)
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*



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