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TMPR4937 Datasheet(PDF) 512 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 512 Page - Toshiba Semiconductor |
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512 / 552 page ![]() Chapter 21 Electrical Characteristics 21-6 21.5.3 SDRAM Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V, CL = 150 pF) Item Symbol Conditions Min. Max. Unit SDCLK[3:0] Cycle Time tCYC_SDCLK CL=50 pF, 16 mA buffer time 7.5 ⎯ ns SDCLK[3:0] High Time tHIGH_SDCLK CL=50 pF, 16 mA buffer time 2.5 ⎯ ns SDCLK[3:0] Low Time tLOW_SDCLK CL=50 pF, 16 mA buffer time 2.5 ⎯ ns SDCLKIN Input Skew tBP When in the Non-bypass mode *4) 0 tCYC_SDCLK – 5.5 ns CL=150 pF, 16 mA buffer, *1) 1.5 6.5 ns ADDR[19:5] Output Delay tVAL_ADDR1 CL= 80 pF, 16 mA buffer, *1) 1.5 5.2 ns SDCS[3:0]* Output Delay tVAL_SDCS CL= 80 pF, 16 mA buffer 1.5 5.2 ns CL=150 pF, 16 mA buffer, *1) 1.5 6.5 ns RAS* Output Delay tVAL_RAS CL= 80 pF, 16 mA buffer, *1) 1.5 5.2 ns CL=150 pF, 16 mA buffer, *3) 1.5 6.5 ns CAS* Output Delay tVAL_CAS CL= 80 pF, 16 mA buffer, *3) 1.5 5.2 ns CL=150 pF, 16 mA buffer, *3) 1.5 6.5 ns WE* Output Delay tVAL_WE CL= 80 pF, 16 mA buffer, *3) 1.5 5.2 ns CL=150 pF, 16 mA buffer 1.5 6.5 ns CKE Output Delay tVAL_CKE CL= 80 pF, 16 mA buffer 1.5 5.2 ns CL= 50 pF, 16 mA buffer, *2) 1.5 6.5 ns DQM[7:0] Output Delay tVAL_DQM CL= 30 pF, 16 mA buffer, *2) 1.5 5.2 ns CL= 50 pF, 16 mA buffer, *2) 1.5 6.5 ns DATA[63:0] Output Delay (H →L, L→H) tVAL_DATA1 CL= 30 pF, 16 mA buffer, *2) 1.5 5.2 ns CL= 50 pF, 16 mA buffer, *2) 1.5 6.5 ns DATA[63:0] Output Delay (Valid → Hi- Z) tVAL_DATA1ZV CL= 30 pF, 16 mA buffer, *2) 1.5 5.2 ns CL= 50 pF, 16 mA buffer, *2) 1.5 6.5 ns DATA[63:0] Output Delay (Valid →Hi-Z) tVAL_DATA1VZ CL= 30 pF, 16 mA buffer, *2) 1.5 5.2 ns DATA[63:0] Input Setup Time tSU_DATA1B When in the Bypass mode 4.0 ⎯ ns DATA[63:0] Input Hold Time tHO_DATA1B When in the Bypass mode 0.5 ⎯ ns DATA[63:0] Input Setup Time tSU_DATA1NB When in the Non-bypass mode 1.0 ⎯ ns DATA[63:0] Input Hold Time tHO_DATA1NB When in the Non bypass mode 1.0 ⎯ ns *1) Becomes a 2-cycle signal when tDACT of SDCTR1 is “1”. *2) Becomes a 2-cycle signal when tSWB of SDCTR1 is “1”. *3) 2-cycle signal For information on 2-cycle operation, see the description in Chapter 9 SDRAM Controller. *4) The MAX value is is tCYC_SDCLK – 5.5 ns. Figure 21.5.3 Timing Diagram: Output Signal and Input Signal when in the Bypass Mode (SDCLK Reference) tVAL_* SDCLK[n] OUTPUT INPUT tHO_* tSU_* outputs valid inputs valid |
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