ADS1294CZXGR datasheet(48/114 Pages) TI2

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GPIOPin

GPIOData(read)

GPIOData(write)

GPIOControl

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

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9.3.2 Digital Functionality

9.3.2.1 GPIO Pins (GPIO[4:1])

The ADS129x have a total of four general-purpose digital input/output (GPIO) pins available in normal operation.

The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits of the

GPIO register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits,

the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the

GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an

output, a write to the GPIOD bit sets the output value.

If configured as inputs, these pins must be driven; do not float these pins. The GPIO pins are set as inputs after

power-on or after a reset. Figure 51 shows the GPIO port structure. If not used, short these pins to DGND.

For example, one configuration is to use GPIO1 as the PACEIN signal, multiplex GPIO2 with RESP_BLK signal,

multiplex GPIO3 with the RESP signal, and multiplex GPIO4 with the RESP_PH signal.

Figure 51. GPIO Port Pin

9.3.2.2 Power-Down Pin (PWDN)

When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin

high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wakeup.

During power down, shut down the external clock to save power.

9.3.2.3 Reset (RESET Pin and Reset Command)

There are two methods to reset the ADS129x: pull the RESET pin low, or send the RESET opcode command

(see the RESET: Reset Registers to Default Values section). Take the RESET pin low to force a reset. Make

sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET

command takes effect on the eighth SCLK falling edge of the opcode command. At reset, 18 tCLK cycles are

required to complete initialization of the configuration registers to the default states and start the conversion

cycle. For more information, see the RESET: Reset Registers to Default Values section. An internal reset is

automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to new values with a

WREG command.

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Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294CZXGR Datasheet(PDF) 48 Page - Texas Instruments