ADS1294CZXGR datasheet(96/114 Pages) TI2

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VCAP1

Supplies

tPOR

(1)(2)

VCAP = 1.1V

1.1V

tBG

(1)

tRST

18 × tCLK

Start using

device

RESET

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

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11 Power Supply Recommendations

The ADS129x have three power supplies: AVDD, AVDD1, and DVDD. For best performance, both AVDD and

AVDD1 must be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients

at fCLK. Therefore, star connect AVDD1 and AVSS1 to AVDD and AVSS. It is important to eliminate noise from

AVDD and AVDD1 that is nonsynchronous with ADS129x operation. Bypass each ADS129x supply with 1-

μF

and 0.1-

μF solid ceramic capacitors. For best performance, place the digital circuits (DSP, microcontrollers,

FPGAs, and so forth) in the system so that the return currents on those devices do not cross the analog return

path of the ADS129x. Power the ADS129x from unipolar or bipolar supplies.

Use surface-mount, low-cost, low-profile, multilayer ceramic-type capacitors for decoupling. In most cases, the

VCAP1 capacitor is also a multilayer ceramic; however, in systems where the board is subjected to high- or low-

frequency vibration, install a nonferroelectric capacitor, such as a tantalum or class 1 capacitor (C0G or NPO).

EIA class 2 and class 3 dielectrics such as (X7R, X5R, X8R, and so forth) are ferroelectric. The piezoelectric

property of these capacitors can appear as electrical noise coming from the capacitor. When using internal

reference, noise on the VCAP1 node results in performance degradation.

11.1 Power-Up Sequencing

Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these

signals low until the power supplies have stabilized, as shown in Figure 105.

Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to

the CLK pin. Wait for time tPOR, then transmit a reset pulse using either the RESET pin or RESET command to

initialize the digital portion of the chip. Issue the reset after tPOR or after the VCAP1 voltage is greater than 1.1 V,

whichever time is longer. Note that:

•

tPOR is described in Table 38.

•

The VCAP1 pin charge time is set by the RC time constant; see Figure 31.

After releasing the RESET pin, program the configuration registers; see the CONFIG1: Configuration Register 1

(address = 01h) (reset = 06h) section for details. The power-up sequence timing is shown in Table 38.

(1)

Timing to reset pulse is tPOR or after tBG, whichever is longer.

(2)

When using an external clock, tPOR timing does not start until CLK is valid.

Figure 105. Power-Up Timing Diagram

Table 38. Timing Requirements for Figure 105

MIN

MAX

UNIT

tPOR

Wait after power up until reset

218

tCLK

tRST

Reset low duration

tCLK

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Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294CZXGR Datasheet(PDF) 96 Page - Texas Instruments

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