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ADS1294CZXGR Datasheet(PDF) 79 Page - Texas Instruments |
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ADS1294CZXGR Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 114 page  ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R www.ti.com SBAS459K – JANUARY 2010 – REVISED AUGUST 2015 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh) The general-purpose I/O register controls the action of the three GPIO pins. When RESP_CTRL[1:0] is in mode 01 and 11, the GPIO2, GPIO3, and GPIO4 pins are not available for use. Figure 87. GPIO: General-Purpose I/O Register 7 6 5 4 3 2 1 0 GPIOD[4:1] GPIOC[4:1] R/W-0h R/W-Fh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30. General-Purpose I/O Field Descriptions Bit Field Type Reset Description 7:4 GPIOD[4:1] R/W 0h GPIO data These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. GPIO is not available in certain respiration modes. 3:0 GPIOC[4:1] R/W Fh GPIO control (corresponding GPIOD) These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input 9.6.1.15 PACE: Pace Detect Register (address = 15h) (reset = 00h) This register provides the pace controls that configure the channel signal used to feed the external pace detect circuitry. See the Pace Detect section for details. Figure 88. PACE: Pace Detect Register 7 6 5 4 3 2 1 0 0 0 0 PACEE[1:0] PACEO[1:0] PD_PACE R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. (For example, CONTROL_REVISION Register) Field Descriptions Bit Field Type Reset Description 7:5 RESERVED R/W 0h Reserved Always write 0h 4:3 PACEE[1:0] R/W 0h Pace even channels These bits control the selection of the even number channels available on TEST_PACE_OUT1. Only one channel may be selected at any time. 00 = Channel 2 01 = Channel 4 10 = Channel 6 (ADS1296, ADS1296R, ADS1298, ADS1298R) 11 = Channel 8 (ADS1298 and ADS1298R) 2:1 PACEO[1:0] R/W 0h Pace odd channels These bits control the selection of the odd number channels available on TEST_PACE_OUT2. Only one channel may be selected at any time. 00 = Channel 1 01 = Channel 3 10 = Channel 5 (ADS1296, ADS1296R, ADS1298, ADS1298R) 11 = Channel 7 (ADS1298, ADS1298R) 0 PD_PACE R/W 0h Pace detect buffer This bit is used to enable/disable the pace detect buffer. 0 = Pace detect buffer turned off 1 = Pace detect buffer turned on Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 79 Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R |
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