ADS1294CZXGR datasheet(59/114 Pages) TI2

59 / 114 page

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

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SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

9.5 Programming

9.5.1 SPI Interface

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls the ADS129x operation. The DRDY output is used as a

status signal to indicate when data are ready. DRDY goes low when new data are available.

9.5.1.1 Chip Select Pin (CS)

Chip select (CS) selects the ADS129x devices for SPI communication. While CS is low, the serial interface is

active. CS must remain low for the entire duration of the serial communication. After the serial communication is

finished, always wait four or more tCLK periods before taking CS high. When CS is taken high, the serial interface

resets, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data

conversion is complete, regardless of whether CS is high or low.

While ADS129x is selected, the device attempts to decode and execute commands every eight serial clocks. If

the device ceases to execute serial commands, it is possible extra clock pulses were presented that placed the

serial interface into an unknown state. To reset the serial interface to a known state, take CS high and back low

again.

9.5.1.2 Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from

the device. The serial clock (SCLK) features a Schmitt-triggered input, and clocks data on the DIN and DOUT

pins into and out of the ADS129x. Even though the input has hysteresis, keep SCLK as clean as possible to

prevent glitches from accidentally forcing a clock event. The absolute maximum limit for SCLK is specified in the

Timing Requirements: Serial Interface table.

While ADS129x is selected (CS = low), the device attempts to decode and execute commands every eight serial

clocks. Therefore, present multiples of eight SCLKs every serial transfer to keep the interface in a normal

operating mode. If the interface ceases to function because of extra serial clocks, reset by toggling CS high and

back low.

For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits

of resolution, and output data rate. For multiple cascaded devices, see the Cascade Configuration section.

Equation 7 shows the calculation for minimum SCLK speed.

tSCLK < (tDR – 4tCLK) / (NBITS × NCHANNELS + 24)

(7)

For example, if the ADS1298 is used at 500-SPS (eight channels, 24-bit resolution), the minimum SCLK speed is

110 kHz.

Retrieve data either by putting the device in RDATAC mode or by issuing a RDATA command for data on

demand. The SCLK rate limitation of Equation 7 also applies to RDATAC. For the RDATA command, the

limitation applies if data must be read between two consecutive DRDY signals. Equation 7 assumes that there

are no other commands issued between data captures.

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ADS1294CZXGR Datasheet(PDF) 59 Page - Texas Instruments