ADS1294CZXGR datasheet(60/114 Pages) TI2

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SCLK

DRDY

DOUT

STAT

24-Bit

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

216SCLKs

DIN

SCLK

Burst Method

SCLK

Continuous Stream Method

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

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Programming (continued)

9.5.1.2.1

SCLK Clocking Methods

As shown in Figure 68, there are two different SCLK clocking methods to satisfy the decode timing specification

shown in Figure 1 for multiple-byte commands.

For SCLK speeds that meet the tSDECODE timing requirement shown in Figure 1, transmit SCLK in a continuous

stream when CS is low. This method is not to be confused with a free-running SCLK, where SCLK operates

when CS is high. Free-running SCLK operation is not supported by this device.

For faster SCLK speeds that do not meet the tSDECODE timing requirement, SCLK is transmitted in 8-bit bursts

with a delay between bursts. The absolute maximum SCLK limit is specified in the Timing Requirements: Serial

Interface table. Figure 68 shows the difference between the two SCLK clocking methods for this device.

Figure 68. SCLK Clocking Methods

9.5.1.3 Data Input Pin (DIN)

The data input pin (DIN) is used along with SCLK to communicate with the ADS129x (opcode commands and

9.5.1.4 Data Output Pin (DOUT)

The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS129x. Data on

DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In

read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line

also indicates when new data are available. Use this feature to minimize the number of connections between the

device and the system controller.

Figure 69 shows the data output protocol for ADS1298.

Figure 69. SPI Bus Data Output for the ADS1298 (Eight Channels)

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Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294CZXGR Datasheet(PDF) 60 Page - Texas Instruments

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