ADS1294CZXGR datasheet(64/114 Pages) TI2

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SCLK

DIN

OPCODE1

OPCODE2

REGDATA1

REGDATA2

DOUT

SCLK

DIN

OPCODE1

OPCODE2

DOUT

REGDATA

REGDATA+1

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

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9.5.2.10 RREG: Read From Register

The RREG opcode command reads register data. The RREG command is a two-byte opcode followed by the

output of the register data. The first byte contains the command opcode and the register address. The second

byte of the opcode specifies the number of registers to read – 1.

First opcode byte: 001r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 72. When

the device is in read data continuous mode, it is necessary to issue a SDATAC command before a RREG

command can be issued. An RREG command can be issued any time. However, because this command is a

multibyte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See

the Serial Clock (SCLK) section for more details. CS must be low for the entire command.

Figure 72. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)

(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)

9.5.2.11 WREG: Write to Register

The WREG opcode command writes register data. The WREG command is a two-byte opcode followed by the

input of the register data. The first byte contains the command opcode and the register address. The second

byte of the opcode specifies the number of registers to write – 1.

First opcode byte: 010r rrrr, where r rrrr is the starting register address.

Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 73. The WREG

command can be issued any time. However, because this command is a multibyte command, there are

restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) section

for more details. CS must be low for the entire command.

Figure 73. WREG Command Example: Write Two Registers Starting from 00h (ID Register)

(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)

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Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294CZXGR Datasheet(PDF) 64 Page - Texas Instruments

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