ADS1294CZXGR datasheet(53/114 Pages) TI2

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SCLK

DOUT

LOFF_STATP[7:0]

LOFF_STATN[7:0]

GPIO[7:4]

SCLK

DRDY

ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R

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SBAS459K – JANUARY 2010 – REVISED AUGUST 2015

The DRDY signal is cleared on the first SCLK falling edge, regardless of the state of CS. Even if no data are

clocked out, the DRDY signal is still cleared. Take this condition into consideration if the SPI bus is used to

communicate with other devices on the same bus. Figure 60 shows a timing diagram for this multiplexing.

Figure 60. DRDY and SCLK Behavior for SPI Bus Multiplexing

9.4.1.3 Data Retrieval

Data retrieval is accomplished in one of two methods:

1. RDATAC: the read data continuous command sets the device mode that reads data continuously without

sending opcodes. See the RDATAC: Read Data Continuous section for more details.

2. RDATA: the read data command reads just one data output from the device. See the RDATA: Read Data

section for more details.

See the SPI Command Definitions section for more details.

The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on

the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. Keep DIN low for the entire read

operation.

9.4.1.3.1

Status Word

The ADS129x data readback is preceded by a status word that provides information on the state of the ADC.

The status word is 24 bits long and contains the values for LOFF_STATP, LOFF_STATN, and part of the GPIO

registers. The content alignment is shown in Figure 61.

Figure 61. Status Word Content

9.4.1.3.2

Readback Length

The number of bits in the data output depends on the number of channels and the number of bits per channel.

The data format for each channel data is twos complement and MSB first. For the ADS129x with 32-kSPS and

64-kSPS data rates, the number of data bits is 24 status bits + 16 bits per channel × 8 channels = 152 bits. For

all other data rates, the number of data bits is 24 status bits + 24 bits per channel × 8 channels = 216 bits. When

channels are powered down using the user-register setting, the corresponding channel output is set to 0.

However, the sequence of channel outputs remains the same. The ADS1294 outputs four channels of datam and

the ADS1296 outputs six channels of data.

The ADS129x also provide a multiple-readback feature. Set the DAISY_IN bit in the CONFIG1 register to 1 for

multiple readbacks. Simply provide additional SCLKs to read data multiple times; the MSB data byte repeats

after reading the last byte.

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Product Folder Links: ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R

ADS1294CZXGR Datasheet(PDF) 53 Page - Texas Instruments

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