TAS5548 datasheet(69/118 Pages) TI2

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TAS5548

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SLES270A – NOVEMBER 2012 – REVISED APRIL 2015

Table 35. PWM Registers Format

D6/D2

D5/D1

D4/D0

FUNCTION

Select channel 1

Select channel 2

Select channel 3

Select channel 4

Select channel 5

Select channel 6

Select channel 7

Select channel 8

7.6.2.19 BD Mode and Ternary - 8 Interchannel Channel Delay (0x38 to 0x3F)

Interchannel delay is used to distribute the switching current of each channel, to ease the peak power draw on

the PSU. It's also used to control the intermodulation between the channels, therefore improving THD in some

cases.

DCLK is the oversampling clock of the PWM.

DCLK on the TAS5548 will be constant, unless some AM avoidance modes are used.

Each channel can have its channel delay set between -128 to +124. (4 DCLK steps value (-32 to +31 over 5

bits))

Channels 0, 1, 2, 3, 4, 5, 6, 7 are mapped into (0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F) with bits

D[7:2] used to program individual DCLK delay. Bit D[1:0] are reserved in each register.

Table 36. Interchannel Delay Register Format (0x38B to 0x3F)

FUNCTION

Minimum absolute delay, 0 DCLK cycles

Maximum positive delay, 31(×4) DCLK cycles

Maximum Negative delay, –32(×4) DCLK cycles

Default Value for channel 0 = -128 DCLK's (–32*4)

Default Value for channel 1 0

Default Value for channel 2 = -64DCLK's (–16*4)

Default Value for channel 3 = 64 DCLK's (16*4)

Default Value for channel 4 = -96 DCLK's (–24*4)

Default Value for channel 5 = 32 DCLK's (8*4)

Default Value for channel 6 = -32 DCLK's (–8*4)

Default Value for channel 7 = 96 DCLK's (24*4)

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