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M58WT032KB Datasheet(PDF) 36 Page - Numonyx B.V |
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M58WT032KB Datasheet(HTML) 36 Page - Numonyx B.V |
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36 / 117 page  Status Register M58WTxxxKT, M58WTxxxKB 36/117 7 Status Register The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register (refer to Section 5.2: Read Status Register command for more details). To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the Status Register during Program and Erase operations, as long as no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 provide information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 provide information on errors. TThey are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the descriptions in the following sections. 7.1 Program/Erase Controller status bit (SR7) The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During program and erase operations the Program/Erase Controller status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the erase status, program status, VPP status and block lock status bits should be tested for errors. |
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