M58WT032KB datasheet(23/117 Pages) NUMONYX

23 / 117 page

M58WTxxxKT, M58WTxxxKB

Command interface - standard commands

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5.6

Block Erase command

The Block Erase command erases a block. It sets all the bits within the selected block to ’1’.

All previous data in the block is lost. If the block is protected then the erase operation aborts,

the data in the block does not change, and the Status Register outputs the error. The Block

Erase command can be issued at any moment, regardless of whether the block has been

programmed or not.

Two bus write cycles are required to issue the command:

●

The first bus cycle sets up the erase command

●

The second latches the block address in the Program/Erase Controller and starts it

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5

are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot

be guaranteed when the erase operation is aborted, the block must be erased again.

Once the command is issued, the device outputs the Status Register data when any

address within the bank is read. At the end of the operation the bank remains in Read

Status Register mode until a Read Array, Read CFI Query, or Read Electronic Signature

command is issued.

During erase operations the bank containing the block being erased only accepts the Read

Array, Read Status Register, Read Electronic Signature, Read CFI Query and the

Program/Erase Suspend commands; all other commands are ignored. Refer to Section 10

for detailed information about simultaneous operations allowed in banks not being erased.

Typical erase times are given in Table 17: Program/erase times and endurance cycles.

See Appendix C, Figure 24: Block erase flowchart and pseudo code for a suggested

flowchart for using the Block Erase command.

5.7

Program command

The memory array can be programmed word-by-word. Only one word in one bank can be

programmed at any one time. If the block is protected, the program operation aborts, the

data in the block does not change, and the Status Register outputs the error.

Two bus write cycles are required to issue the Program command:

●

The first bus cycle sets up the Program command

●

The second latches the address and the data to be written and starts the

Program/Erase Controller

After programming has started, read operations in the bank being programmed output the

Status Register content.

During Program operations the bank being programmed only accepts the Read Array, Read

Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase

Suspend commands. Refer to Section 10 for detailed information about simultaneous

operations allowed in banks not being programmed. Typical program times are given in

Table 17: Program/erase times and endurance cycles.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the

program operation is aborted, the memory location must be reprogrammed.

See Appendix C, Figure 20: Program flowchart and pseudo code for the flowchart for using

the Program command.

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