M58WT032KB datasheet(33/117 Pages) NUMONYX

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M58WTxxxKT, M58WTxxxKB

Command interface - factory program commands

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6.4

Quadruple Enhanced Factory Program command

The Quadruple Enhanced Factory Program command programs one or more pages of four

adjacent words in parallel. The four words must only differ for the addresses A0 and A1.

VPP must be set to VPPH during the Quadruple Enhanced Factory Program, otherwise the

command is ignored and the Status Register does not output any error.

Dual operations are not supported during Quadruple Enhanced Factory Program operations

and the command cannot be suspended.

If the block is protected then the Quadruple Enhanced Factory Program operation aborts,

the data in the block does not change, and the Status Register outputs the error.

The Quadruple Enhanced Factory Program command has four phases: the setup phase,

the load phase where the data is loaded into the buffer, the combined program and verify

phase where the loaded data is programmed to the memory and then automatically checked

and reprogrammed if necessary and the exit phase. Unlike the Enhanced Factory Program it

is not necessary to resubmit the data for the verify phase. The load phase and the program

and verify phase can be repeated to program any number of pages within the block.

6.4.1

Setup phase

The Quadruple Enhanced Factory Program command requires one bus write operation to

initiate the load phase. After the setup command is issued, read operations output the

Status Register data. The Read Status Register command must not be issued or it is

interpreted as data to program.

6.4.2

Load phase

The load phase requires 4 cycles to load the data (refer to Table 8: Factory program

commands and Figure 29: Quadruple enhanced factory program flowchart). Once the first

word of each page is written it is impossible to exit the load phase until all four words have

been written.

Two successive steps are required to issue and execute the load phase of the Quadruple

Enhanced Factory Program command.

Use one bus write operation to latch the start address and the first word of the first

page to be programmed, where the start address is the location of the first data to be

programmed. For subsequent pages the first word address can remain the start

address (in which case the next page is programmed) or can be any address in the

same block. If any address with data FFFFh is given that is not in the same block as the

start address, the device enters the exit phase. For the first load phase Status Register

bit SR7 should be read after the first word has been issued to check that the command

has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent load

phases.

Each subsequent word to be programmed is latched with a new bus write operation.

The address is only checked for the first word of each page as the order of the words to

be programmed is fixed.

The memory is now set to enter the program and verify phase.

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