M58WT032KB datasheet(31/117 Pages) NUMONYX

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M58WTxxxKT, M58WTxxxKB

Command interface - factory program commands

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6.3

Enhanced Factory Program command

The Enhanced Factory Program command programs large streams of data within any one

block. It greatly reduces the total programming time when a large number of words are

written to a block at any one time.

Dual operations are not supported during the Enhanced Factory Program operation and the

command cannot be suspended.

For optimum performance the Enhanced Factory Program commands should be limited to a

maximum of 10 program/erase cycles per block. If this limit is exceeded the internal

algorithm continues to work properly but some degradation in performance is possible.

Typical program times are given in Table 17

If the block is protected then the Enhanced Factory Program operation aborts, the data in

the block does not change, and the Status Register outputs the error.

The Enhanced Factory Program command has four phases: the setup phase, the program

phase to program the data to the memory, the verify phase to check that the data has been

correctly programmed and reprogram if necessary and the exit phase. Refer to Table 8:

Factory program commands, and Figure 28: Enhanced factory program flowchart.

6.3.1

Setup phase

The Enhanced Factory Program command requires two bus write operations to initiate the

command:

●

The first bus cycle sets up the Enhanced Factory Program command

●

The second bus cycle confirms the command.

The Status Register P/EC bit SR7 should be read to check that the P/EC is ready. After the

confirm command is issued, read operations output the Status Register data. The read

Status Register command must not be issued or it is interpreted as data to program.

If the second bus cycle is not EFP confirm (D0h), Status Register bits SR4 and SR5 are set

and the command aborts.

VPP value must be in the VPPH range during the confirm command, otherwise SR4 and SR3

are set and command are aborted.

6.3.2

Program phase

The program phase requires n+1 cycles, where n is the number of words (refer to Table 8:

Factory program commands, and Figure 28: Enhanced factory program flowchart).

Three successive steps are required to issue and execute the program phase of the

command:

Use one bus write operation to latch the start address and the first word to be

programmed, where the start address is the location of the first data to be

programmed. The Status Register Bank Write Status bit SR0 should be read to check

that the P/EC is ready for the next word.

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