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M58WT032KB Datasheet(PDF) 32 Page - Numonyx B.V |
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M58WT032KB Datasheet(HTML) 32 Page - Numonyx B.V |
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32 / 117 page  Command interface - factory program commands M58WTxxxKT, M58WTxxxKB 32/117 2. Each subsequent word to be programmed is latched with a new bus write operation. The address can either remain the start address, in which case the P/EC increments the address location. Or the address can be incremented, in which case the P/EC jumps to the new address. If any address is given that is not in the same block as the start address with data FFFFh, the program phase terminates and the verify phase begins. The Status Register bit SR0 should be read between each bus write cycle to check that the P/EC is ready for the next word. 3. Finally, after all words have been programmed, write one bus write operation with data FFFFh to any address outside the block containing the start address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the verify phase. 6.3.3 Verify phase The verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the program phase and reprograms the memory location, if necessary. Three successive steps are required to execute the verify phase of the command: 1. Use one bus write operation to latch the start address and the first word to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next word. 2. Each subsequent word to be verified is latched with a new bus write operation. The words must be written in the same order as in the program phase. The address can remain the start address or be incremented. If any address that is not in the same block as the start address is given with data FFFFh, the verify phase terminates. Status Register bit SR0 should be read to check that the P/EC is ready for the next word. 3. Finally, after all words have been verified, write one bus write operation with data FFFFh to any address outside the block containing the start address, to terminate the verify phase. If the verify phase is successfully completed, the memory remains in read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error is signaled in the Status Register. 6.3.4 Exit phase Status Register P/EC bit SR7 set to ‘1’ indicates that the device has returned to read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See Section 7: Status Register for more details. |
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