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M58WT032KB Datasheet(PDF) 41 Page - Numonyx B.V |
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M58WT032KB Datasheet(HTML) 41 Page - Numonyx B.V |
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41 / 117 page  M58WTxxxKT, M58WTxxxKB Configuration Register 41/117 8 Configuration Register The Configuration Register configures the type of bus access that the memory performs. Refer to Section 9: Read modes for details on read operations. The Configuration Register is set through the command interface. After a reset or power-up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 11. They specify the selection of the burst length, burst type, burst X latency, and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. 8.1 Read select bit (CR15) The read select bit, CR15, switches between asynchronous and synchronous bus read operations. When the read select bit is set to ’1’, read operations are asynchronous; when the read select bit is set to ’0’, read operations are synchronous. Synchronous burst read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the read select bit is set to’1’ for asynchronous access. 8.2 X latency bits (CR13-CR11) The X latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X latency bits can only assume the values in Table 11: Configuration Register. Table 10shows how to set the X latency parameter, taking into account the speed class of the device and the frequency used to read the Flash memory in synchronous mode. 8.3 Wait polarity bit (CR10) In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The wait polarity bit is used to set the polarity of the Wait signal. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait polarity bit is set to ‘1’ the Wait signal is active High. Table 10. Latency settings fmax tKmin X latency min 30 MHz 33 ns 2 40 MHz 25 ns 3 52 MHz 19 ns 4 |
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