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M58WT032KB Datasheet(PDF) 50 Page - Numonyx B.V

Part # M58WT032KB
Description  32- and 64-Mbit (횞16, multiple bank, burst) 1.8 V core, 3.0 V I/O supply Flash memories
PDF  117 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M58WT032KB Datasheet(HTML) 50 Page - Numonyx B.V

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Read modes
M58WTxxxKT, M58WTxxxKB
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9.3
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output), or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when E is low and the current address
has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal
is then halted at VIH or at VIL, and G goes high.
When G becomes low again and the clock signal restarts, the synchronous burst read
operation is resumed exactly where it stopped.
WAIT being gated by E remains active and does not revert to high-impedance when G goes
high. Therefore, if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the Flash memory should not be directly
connected to the system’s READY signal.
See Table 24: Synchronous read AC characteristics and Figure 14: Synchronous burst read
suspend AC waveforms for details.
9.4
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations
except that only the first data output after the X latency is valid. Synchronous single reads
are used to read the electronic signature, Status Register, CFI, block protection status,
Configuration Register status or Protection Register status. When the addressed bank is in
read CFI, read Status Register or read electronic signature mode, the WAIT signal is always
asserted.
See Table 24: Synchronous read AC characteristics and Figure 13: Single synchronous
read AC waveforms for details.



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