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M58WT032KB Datasheet(PDF) 16 Page - Numonyx B.V |
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M58WT032KB Datasheet(HTML) 16 Page - Numonyx B.V |
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16 / 117 page  Signal descriptions M58WTxxxKT, M58WTxxxKB 16/117 2.7 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current IDD2. Refer to Table 21: DC characteristics - currents for the value of IDD2. After Reset all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Upon exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. 2.8 Latch Enable (L) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. 2.9 Clock (K) The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ‘don't care’ during asynchronous read and in write operations. 2.10 Wait (WAIT) Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is not gated by Output Enable. 2.11 VDD supply voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). 2.12 VDDQ supply voltage VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of VDD. |
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