M58WT032KB datasheet(25/117 Pages) NUMONYX

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M58WTxxxKT, M58WTxxxKB

Command interface - standard commands

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5.10

Protection Register Program command

The Protection Register Program command programs the 128-bit user OTP segment of the

Protection Register and the Protection Register lock. The segment is programmed 16 bits at

a time. When shipped, all bits in the segment are set to ‘1’. The user can only program the

bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command:

●

The first bus cycle sets up the Protection Register Program command.

●

The second latches the address and the data to be written to the Protection Register

and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The segment can be protected by programming bit 1 of the Protection Lock Register (see

Figure 5: Protection Register memory map). Attempting to program a previously protected

Protection Register results in a Status Register error. The protection of the Protection

operations between the parameter bank and the Protection Register memory space are not

allowed (see Table 15: Dual operation limitations).

5.11

The Set Configuration Register command

The Set Configuration Register command writes a new value to the Configuration Register,

which defines the burst length, type, X latency, synchronous/asynchronous read mode, and

the valid Clock edge configuration.

Two bus write cycles are required to issue the Set Configuration Register command:

●

The first cycle writes the setup command and the address corresponding to the

Configuration Register content.

●

The second cycle writes the Configuration Register data and the confirm command.

Read operations output the memory array content after the Set Configuration Register

command is issued.

The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1

on A1, etc.; the other address bits are ignored.

5.12

Block Lock command

The Block Lock command locks a block and prevents program or erase operations from

changing the data in it. All blocks are locked at power-up or reset.

Two bus write cycles are required to issue the Block Lock command:

●

The first bus cycle sets up the Block Lock command.

●

The second bus write cycle latches the block address.

The lock status can be monitored for each block using the Read Electronic Signature

command. Table 16 shows the lock status after issuing a Block Lock command.

The block lock bits are volatile; once set they remain set until a hardware reset or power-

down/power-up. They are cleared by a Block Unlock command. Refer to Section 11: Block

locking for a detailed explanation. See Appendix C, Figure 26: Locking operations flowchart

and pseudo code for a flowchart for using the Lock command.

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