M58WT032KB datasheet(98/117 Pages) NUMONYX

98 / 117 page

Common Flash interface

M58WTxxxKT, M58WTxxxKB

98/117

(P+36)h = 6Fh

07h

Bank Region 2 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+37)h = 70h

00h

(P+38)h = 71h

20h

(P+39)h = 72h

00h

(P+3A)h = 73h

64h

Bank Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

(P+3B)h = 74h

00h

(P+3C)h = 75h

01h

Bank Region 2 (Erase Block Type 2): BIts per cell, internal

ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+3D)h = 76h

03h

Bank Region 2 (Erase Block Type 2): page mode and

synchronous mode capabilities (defined in Table 40)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+3E)h = 77h

Feature Space definitions

(P+3F)h = 78h

Reserved

The variable P is a pointer which is defined at CFI offset 15h.

Applies to M58WT032KB.

Applies to M58WT064KB.

Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.

Table 43.

Bank and Erase block region 2 information(1) (continued)

M58WT032KT,

M58WT064KT

M58WT032KB,

M58WT064KB

Description

Offset

Data

Offset

Data

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