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M58WT032KB Datasheet(PDF) 43 Page - Numonyx B.V |
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M58WT032KB Datasheet(HTML) 43 Page - Numonyx B.V |
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43 / 117 page  M58WTxxxKT, M58WTxxxKB Configuration Register 43/117 8.9 Burst length bits (CR2-CR0) The burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1, 2 or 3 positions from the 4-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary to indicate that the device needs an internal delay to read the successive words in the array. WAIT is asserted only once during a continuous burst access. See also Table 12: Burst type definition. CR14, CR5 and CR4 are reserved for future use. |
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