M58WT032KB datasheet(8/117 Pages) NUMONYX

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Description

M58WTxxxKT, M58WTxxxKB

8/117

Description

The M58WT032KT/B and M58WT064KT/B are 32 Mbit (2 Mbit ×16) and 64 Mbit (4 Mbit

×16) non-volatile Flash memories, respectively. They can be erased electrically at block

level and programmed in-system on a word-by-word basis using a 1.7 V to 2 V VDD supply

for the circuitry and a 2.7 V to 3.3 V VDDQ supply for the input/output pins. An optional 9 V

VPP power supply is provided to speed up customer programming.

M58WTxxxKT/B is the collective name for all these devices. They feature an asymmetrical

block architecture.

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The M58WT032KT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There

are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank

containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.

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The M58WT064KT/B has an array of 135 blocks, and is divided into 4 Mbit banks.

There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter

bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.

The multiple bank architecture allows dual operations. While programming or erasing in one

bank, read operations are possible in other banks. Only one bank at a time is allowed to be

in program or erase mode. It is possible to perform burst reads that cross bank boundaries.

The bank architectures are summarized in Table 2 and Table 3 and the memory maps are

shown in Figure 3 and Figure 4. The parameter blocks are located at the top of the memory

address space for the M58WT032KT and M58WT064KT, and at the bottom for the

M58WT032KB and M58WT064KB.

Each block can be erased separately. Erase can be suspended to perform program in any

other block, and then resumed. Program can be suspended to read data in any other block

and then resumed. Each block can be programmed and erased over 100 000 cycles using

the supply voltage VDD. Two enhanced factory programming commands are available to

speed up programming.

Program and erase commands are written to the command interface of the memory. An

internal Program/Erase Controller manages the timings necessary for program and erase

operations. The end of a program or erase operation can be detected and any error

conditions identified in the Status Register. The command set required to control the

memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the

memory array; at power-up the device is configured for asynchronous read. In synchronous

burst mode, data is output on each clock cycle at frequencies of up to 52 MHz. The

synchronous burst read operation can be suspended and resumed.

The device features an automatic standby mode. When the bus is inactive during

asynchronous read operations, the device automatically switches to the automatic standby

mode. In this condition the power consumption is reduced to the standby value IDD4 and the

outputs are still driven.

M58WT032KB Datasheet(PDF) 8 Page - Numonyx B.V

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