M58WT032KB datasheet(113/117 Pages) NUMONYX

113 / 117 page

M58WTxxxKT, M58WTxxxKB

Command interface state tables

113/117

Table 45.

Command interface states - modify table, next output(1)

Current CI State

Command Input(2)

Read

Array(3)

(FFh)

DWP, QWP

Setup(4)(5)

(35h, 56h)

Block

Erase

Setup(4)(5)

(20h)

EFP

Setup

(30h)

Quad-

EFP

Setup

(75h)

Erase Confirm

P/E Resume,

Block Unlock

confirm, EFP

Confirm (D0h)

Program/

Erase

Suspend

(B0h)

Read

Status

(70h)

Clear Status

(50h)

Read Electronic

signature, Read

CFI Query (90h,

98h)

Program Setup

Status Register

Erase Setup

OTP Setup

Program Setup in

Erase Suspend

EFP Setup

EFP Busy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup

Lock/CR Setup in

Erase Suspend

OTP Busy

Array

Status Register

Output Unchanged

Status

Output

Unchanged

Status Register

Ready

Electronic

Signature/CFI

Program Busy

Erase Busy

Program/Erase

Suspend

Program Busy in

Erase Suspend

Program Suspend

in Erase Suspend

Illegal State

Output Unchanged

CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple

Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase

Controller, IS = Illegal State, ES = Erase suspend, PS = Program suspend.

The output state shows the type of data that appears at the outputs if the bank address is the same as the command

address. A bank can be placed in read array, Read Status Register, Read Electronic Signature or Read CFI Query mode,

depending on the command issued. Each bank remains in its last output state until a new command is issued. The next

state does not depend on the bank’s output state.

At Power-Up, all banks are in read array mode. A Read Array command issued to a busy bank, results in undetermined

data output.

The two cycle command should be issued to the same bank address.

If the P/EC is active, both cycles are ignored.

The Clear Status Register command clears the Status Register error bits except when the P/EC is busy or suspended.

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