F24 datasheet(107/210 Pages) RENESAS

107 / 210 page

RL78/F23, F24

4. ELECTRICAL SPECIFICATIONS (GRADE 4)

R01DS0446EJ0120 Rev.1.20

Page 107 of 207

Dec 31, 2025

4.3.2 Supply Current Characteristics

(1)

RL78/F24

(TA = -40 to +125

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(1/2)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply

current

Note 1

IDD1

Operating

mode

Normal

operation

Note 2

High-speed on-

chip oscillator

clock operation

fIH = 80 MHz

fCLK = 40 MHz

Notes 3, 4

10.8

20.0

fIH = 40 MHz

fCLK = fIH Notes 3, 4

10.1

18.3

fIH = 2 MHz

fCLK = fIH Notes 3, 4

1.7

3.4

Resonator

operation

fMX = 20 MHz

fCLK = fMX Notes 3, 5

5.6

10.3

fMX = 2 MHz

fCLK = fMX Notes 3, 5

1.5

3.1

Resonator

operation

(PLL operation)

(PLL input clock

= fMX)

fPLL = 80 MHz,

fMX = 20 MHz

fCLK = 40 MHz

Notes 3, 6

10.6

20.0

fPLL = 40 MHz,

fMX = 20 MHz

fCLK = 40 MHz

Notes 3, 6

10.2

18.3

fPLL = 40 MHz,

fMX = 4 MHz

fCLK = 40 MHz

Notes 3, 6

9.9

17.8

Subsystem

clock operation

fSUB = 32.768

kHz

fCLK = fSUB Note 7

7.6

500

µA

Low-speed on-

chip oscillator

clock operation

fIL = 15 kHz

fCLK = fIL Note 8

4.2

500

µA

Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input

pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on-

chip pull-up/pull-down resistors.

2. Current drawn when all the CPU instructions are executed.

3. The values below the MAX. column include the peripheral operation current (except for background operation

(BGO)). However, the LVD circuit, A/D converter, D/A converter, and comparator are stopped.

4. When high-speed system clock, subsystem clock, PLL clock, and low-speed on-chip oscillator clock are

stopped.

5. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock

are stopped.

6. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped.

7. When high-speed system clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip

oscillator are stopped, and with setting of ADSLP = 1.

8. When high-speed system clock, subsystem clock, PLL clock, and high-speed on-chip oscillator clock are

stopped, and with setting of ADSLP = 1.

Remarks 1. fMX: High-speed system clock frequency

2. fSUB: Subsystem clock frequency

3. fPLL: PLL clock frequency

4. fIH: High-speed on-chip oscillator clock frequency

5. fIL: Low-speed on-chip oscillator clock frequency

6. fCLK: CPU/peripheral hardware clock frequency

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