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F24 Datasheet(PDF) 184 Page - Renesas Technology Corp |
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F24 Datasheet(HTML) 184 Page - Renesas Technology Corp |
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184 / 210 page  RL78/F23, F24 5. ELECTRICAL SPECIFICATIONS (GRADE 5) R01DS0446EJ0120 Rev.1.20 Page 184 of 207 Dec 31, 2025 CSI mode connection diagram (during communication at different potential) Caution Select the TTL input buffer for the SIp, SCKp and SSIp pins and N-ch open-drain output mode for the SOp pin. Remarks 1. Rb [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1) 3. AC characteristics of the serial array unit during communication at different potential in CSI mode are measured with the VIH and VIL below: When 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V User's device RL78 microcontroller SCKp SSIp SCK SI Vb Rb SOp SIp SO ＜ Slave＞ SSO |
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