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C511 Datasheet(PDF) 121 Page - Siemens Semiconductor Group |
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C511 Datasheet(HTML) 121 Page - Siemens Semiconductor Group |
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121 / 128 page ![]() Semiconductor Group 10-9 Device Specifications Figure 10-4 SSC Timing Figure 10-5 External Clock Drive at XTAL1 Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. MCT00033 t CHCX t CLCX CHCL t CLCH t V CC t CLCL - 0.5V 0.45V CC 0.7 V V - 0.1 CC 0.2 |
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