C511 datasheet(117/128 Pages) SIEMENS

117 / 128 page

Semiconductor Group

10-5

Device Specifications

10.3.2

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

12 MHz

Clock

Variable Clock

CLCL = 3.5 MHz to 12 MHz

min.

max.

min.

max.

RD pulse width

RLRH

400

–

CLCL – 100

–

WR pulse width

WLWH

400

–

CLCL – 100

–

Address hold after ALE

LLAX2

132

–

CLCL –35

–

RD to valid data in

RLDV

–

252

–

CLCL – 165

Data hold after RD

RHDX

–

0–ns

Data float after RD

RHDZ

–97

–

CLCL –70

ALE to valid data in

LLDV

–

517

–

CLCL – 150

Address to valid data in

AVDV

–

585

–

CLCL – 165

ALE to WR or RD

LLWL

200

300

CLCL –50

CLCL +50

Address valid to WR or RD

AVWL

203

–

CLCL – 130

–

WR or RD high to ALE high

WHLH

123

CLCL –40

CLCL +40

Data valid to WR transition

QVWX

–

CLCL –50

–

Data setup before WR

QVWH

433

–

CLCL – 150

–

Data hold after WR

WHQX

–

CLCL –50

–

Address float after RD

RLAZ

–

–0ns

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