C167CS datasheet(122/517 Pages) INFINEON

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C167CS

Derivatives

Clock Generation

User’s Manual

6-4

V2.0, 2000-07

6.2

Frequency Control

The CPU clock is generated from the oscillator clock in either of two software selectable

ways:

The basic clock is the standard operating clock for the C167CS and is required to

deliver the intended maximum performance. The clock configuration in register RP0H

(bitfield CLKCFG = RP0H.7-5) determines one of three possible basic clock generation

modes:

• Direct Drive: the oscillator clock is directly fed to the controller hardware.

• Prescaler: the oscillator clock is divided by 2 to achieve a 50% duty cycle.

• PLL: the oscillator clock is multiplied by a configurable factor of F = 1.5 … 5.

The Slow Down clock is the oscillator clock divided by a programmable factor of

1 … 32 (additional 2:1 divider in prescaler mode). This alternate possibility runs the

C167CS at a lower frequency (depending on the programmed slow down factor) and

thus greatly reduces its power consumption.

Figure 6-4

Frequency Control Paths

Note: The configuration register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H) after a long hardware reset, i.e. bitfield CLKCFG

represents the logic levels on pins P0.15-13 (P0H.7-5).

MCD04458

Configuration

PLL

SDD

2:1

CPU Clock

CPU

Oscillator

Clock

OSC

OWD

Software

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