C167CS datasheet(126/517 Pages) INFINEON

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C167CS

Derivatives

Clock Generation

User’s Manual

6-8

V2.0, 2000-07

6.3

Oscillator Watchdog

The C167CS provides an Oscillator Watchdog (OWD) which monitors the clock signal

fed to input XTAL1 of the on-chip oscillator (either with a crystal or via external clock

drive) in prescaler or direct drive mode (not if the PLL provides the basic clock). For this

operation the PLL provides a clock signal (base frequency) which is used to supervise

transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock.

When the expected oscillator clock transitions are missing the OWD activates the PLL

Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal instead of

the selected oscillator clock (see Figure 6-4). Under these circumstances the PLL will

oscillate with its base frequency.

In direct drive mode the PLL base frequency is used directly (

fCPU = 2 … 5 MHz).

In prescaler mode the PLL base frequency is divided by 2 (

fCPU = 1 … 2.5 MHz).

If the oscillator clock fails while the PLL provides the basic clock the system will be

supplied with the PLL base frequency anyway.

With this PLL clock signal the CPU can either execute a controlled shutdown sequence

bringing the system into a defined and safe idle state, or it can provide an emergency

operation of the system with reduced performance based on this (normally slower)

emergency clock.

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.

In this case the PLL remains idle and provides no clock signal, while the CPU clock

signal is derived directly from the oscillator clock or via prescaler or SDD. Also no

interrupt request will be generated in case of a missing oscillator clock.

Note: At the end of an external reset bit OWDDIS reflects the inverted level of pin RD at

that time. Thus the oscillator watchdog may also be disabled via hardware by

(externally) pulling the RD line low upon a reset, similar to the standard reset

configuration via PORT0.

The oscillator watchdog cannot provide full security while the CPU clock signal is

generated by the SlowDown Divider, because the OWD cannot switch to the PLL clock

in this case (see Figure 6-4). OWD interrupts are only recognizable if

fOSC is still

available (e.g. input frequency too low or intermittent failure only).

A broken crystal cannot be detected by software (OWD interrupt server) as no SDD

clock is available in such a case.

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