C167CS datasheet(124/517 Pages) INFINEON

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C167CS

Derivatives

Clock Generation

User’s Manual

6-6

V2.0, 2000-07

Direct Drive

When direct drive is configured (CLKCFG = 011B) the C167CS’s clock system is directly

fed from the external clock input, i.e.

fCPU = fOSC. This allows operation of the C167CS

with a reasonably small fundamental mode crystal. The specified minimum values for the

CPU clock phases (TCLs) must be respected. Therefore the maximum input clock

frequency depends on the clock signal’s duty cycle.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001B) the C167CS’s input clock is

divided by 2 to generate then CPU clock signal, i.e.

fCPU = fOSC / 2. This requires the

oscillator (or input clock) to run on 2 times the intended operating frequency but

guarantees a 50% duty cycle for the internal clock system independent of the input clock

signal’s waveform.

PLL Operation

When PLL operation is configured (via CLKCFG) the C167CS’s input clock is fed to the

on-chip phase locked loop circuit which multiplies its frequency by a factor of F =1.5 …5

(selectable via CLKCFG, see Table 6-1) and generates a CPU clock signal with 50%

duty cycle, i.e.

fCPU = fOSC × F.

The on-chip PLL circuit allows operation of the C167CS on a low frequency external

clock while still providing maximum performance. The PLL also provides fail safe

mechanisms which allow the detection of frequency deviations and the execution of

emergency actions in case of an external clock failure.

When the PLL detects a missing input clock signal it generates an interrupt request. This

warning interrupt indicates that the PLL frequency is no more locked, i.e. no more stable.

This occurs when the input clock is unstable and especially when the input clock fails

completely, e.g. due to a broken crystal. In this case the synchronization mechanism will

reduce the PLL output frequency down to the PLL’s base frequency (2 … 5 MHz). The

base frequency is still generated and allows the CPU to execute emergency actions in

case of a loss of the external clock.

On power-up the PLL provides a stable clock signal within ca. 1 ms after

VDD has

reached the specified valid range, even if there is no external clock signal (in this case

the PLL will run on its base frequency of 2 … 5 MHz). The PLL starts synchronizing with

the external clock signal as soon as it is available. Within ca. 1 ms after stable

oscillations of the external clock within the specified frequency range the PLL will be

synchronous with this clock at a frequency of F

× f

OSC, i.e. the PLL locks to the external

clock.

When PLL operation is selected the CPU clock is a selectable multiple of the oscillator

frequency, i.e. the input frequency.

Table 6-1 lists the possible selections.

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