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C167CS Datasheet(PDF) 146 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 146 Page - Infineon Technologies AG |
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146 / 517 page  C167CS Derivatives Parallel Ports User’s Manual 7-19 V2.0, 2000-07 PORT1 Digital Input Control The pins of P1L may be used for both digital an analog input. By setting the respective bit in register P1DIDIS the digital input stage of the respective P1L pin can be disconnected from the pin. This is recommended when the pin is to be used as analog input, as it reduces the current through the digital input stage and prevents it from toggling while the (analog) input level is between the digital low and high thresholds. So the consumed power and the generated noise can be reduced. After reset all digital input stages are enabled. Figure 7-9 shows the structure of PORT1 pins. The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port latch input. P1DIDIS P1L Digital Inp. Disable Reg. SFR (FEA4H/52H) Reset Value: 0000H 15 14 13 12 11 10 9876 543210 P1D .7 P1D .6 P1D .5 P1D .4 P1D .3 P1D .2 P1D .1 P1D .0 - - - - - - - - rw rw rw rw rw rw rw rw Bit Function P1D.y Port P1L Bit y Digital Input Control 0: Digital input stage connected to port line P1L.y 1: Digital input stage disconnected from port line P1L.y When being read or used as alternate input this line appears as ‘1’. |
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