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4556 Datasheet(PDF) 43 Page - Renesas Technology Corp |
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4556 Datasheet(HTML) 43 Page - Renesas Technology Corp |
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43 / 145 page ![]() Rev.3.02 Dec 22, 2006 page 43 of 142 REJ03B0025-0302 4556 Group Fig. 33 LCD controller/driver Common driver Bias control Multiplexer Selector RAM Segment driver Selector RAM COM3 COM2 COM1 COM0 Decoder SEG28 1/2,1/3,1/4 counter LCD clock (from timer block) L10 L11 L12 L13 Register A LCD ON/ OFF control Control signal SEG0/VLC3 SEG17 ......... ... ... Segment driver ... SEG1 /VLC2 SEG2/VLC1 SEG0 to SEG2 output L20 L21 L22 L23 r r r r r r to SEG10 SEG3 to (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel correspond- ing to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage differ- ence between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a dis- play pixel turns off because every segment output pin and common output pin becomes VLC3 level. Fig. 34 LCD RAM map Z X Y Bits 8 9 10 11 12 13 14 15 COM 1 2 3 21 0 3 21 0 3 21 0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 SEG9 SEG10 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG9 SEG10 SEG9 SEG10 SEG0 SEG0 SEG0 SEG0 SEG8 SEG17 SEG18 SEG19 SEG8 SEG8 SEG8 SEG9 SEG10 SEG17 SEG18 SEG19 SEG17 SEG18 SEG19 SEG17 SEG18 SEG19 0 1 Note: The area marked “ ” is not the LCD display RAM. SEG21 SEG22 SEG23 SEG20 3 3 21 0 COM3 COM2 COM1 COM0 SEG25 SEG26 SEG27 SEG24 SEG28 SEG21 SEG22 SEG23 SEG20 SEG21 SEG22 SEG23 SEG20 SEG21 SEG22 SEG23 SEG20 SEG25 SEG26 SEG27 SEG24 SEG28 SEG25 SEG26 SEG27 SEG24 SEG28 SEG25 SEG26 SEG27 SEG24 SEG28 |
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