4556 datasheet(24/145 Pages) RENESAS

24 / 145 page

Rev.3.02

Dec 22, 2006

page 24 of 142

REJ03B0025-0302

4556 Group

Fig. 16 Interrupt sequence

T1F,T2F,T3F

INT

EXF0

q When an interrupt request flag is set after its interrupt is enabled (Note 1)

System clock

(STCK)

The program starts

from the interrupt

address.

Interrupt enabled state

1 machine cycle

EI instruction execution cycle

Interrupt enable

flag (INTE)

Retaining level of system

clock for 4 periods or more

is necessary.

Interrupt disabled state

External

interrupt

Timer 1,

Timer 2,

Timer 3

interrupts

Interrupt activated

condition is satisfied.

Notes 1: The address is stacked to the last cycle.

2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Flag cleared

2 to 3 machine cycles

(Notes 1, 2)

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt en-

able bits (V10, V12, V13, V20), and interrupt request flag are “1.”

The interrupt actually occurs 2 to 3 machine cycles after the cycle

in which all three conditions are satisfied. The interrupt occurs after

3 machine cycles only when the three interrupt conditions are sat-

isfied on execution of other than one-cycle instructions (Refer to

Figure 16).

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