SH7201 datasheet(37/1196 Pages) RENESAS

37 / 1196 page

Section 1 Overview

Rev. 2.00 Sep. 07, 2007 Page 9 of 1164

REJ09B0321-0200

1.3

Block Diagram

The block diagram of this LSI is shown in figure 1.1.

RES input

MRES input

NMI input

IRQ input

PINT input

Timer pulse I/O

Compare match output

External counter clock input

External counter reset input

RTC_X1 input

RTC_X2 output

Serial I/O

I2C bus I/O

Analog input

ADTRG input

Analog output

JTAG I/O

Serial I/O

Audio clock input

CAN bus I/O

SH-2A CPU

core

Floating-point

unit (FPU)

Instruction cache

memory (8 kbytes)

Operand cache

memory (8 kbytes)

Cache controller

On-chip

RAM

(32 kbytes)

User break

controller

(UBC)

CPU instruction fetch bus (F bus)

CPU memory access bus (M bus)

Internal bus (I bus)

AUDRST input

AUDSYNC input

AUDCK input

AUDMD input

AUDATA I/O

Advanced user

debugger-II

(AUD-II)

UBCTRG

output

Bus bridge

External

bus I/O

External bus

width

mode input

Bus state

controller

(BSC)

On-chip

peripheral

module bus 1

controller

On-chip

peripheral

module bus 2

controller

Bus

monitor

Direct memory

access controller

(DMAC)

DREQ input

DACK output

DACT output

DTEND output

On-chip peripheral

module bus 1

On-chip peripheral module bus 2

Pin function

controller

(PFC)

I/O port

Clock pulse

generator

(CPG)

Watchdog

timer

(WDT)

Interrupt

controller

(INTC)

Multi-function

timer pulse

unit 2

(MTU2)

8-bit timer

(TMR)

Realtime

clock

(RTC)

General I/O

EXTAL input

XTAL output

CKIO I/O

Clock mode input

WDTOVF output

Internal CPU bus

Internal DMA write bus

Internal DMA read bus

Port

User debugging

interface

(H-UDI)

Power-down

mode control

D/A

converter

(DAC)

A/D

converter

(ADC)

Controller

area network

(RCAN-ET)

Serial sound

interface

(SSI)

I2C bus

interface 3

(IIC3)

Serial

communication

interface with

FIFO (SCIF)

CPU bus

(C bus)

Figure 1.1 Block Diagram

SH7201 Datasheet(PDF) 37 Page - Renesas Technology Corp

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