SH7201 datasheet(43/1196 Pages) RENESAS

43 / 1196 page

Section 1 Overview

Rev. 2.00 Sep. 07, 2007 Page 15 of 1164

REJ09B0321-0200

Classification

Symbol

I/O

Name

Function

DREQ3 to

DREQ0

DMA-transfer

request

Input pins to receive external

requests for DMA transfer

Direct memory

access controller

(DMAC)

DACK3 to

DACK0

DMA-transfer

request

acknowledge

Output pins for signals indicating

acknowledge of external requests

from external devices

DACT3 to

DACT0

DMA-transfer

request active

Output pins for signals indicating

DMA active in response to external

requests from external devices

DTEND3 to

DTEND0

DMA-transfer end

output

Output pins for DMA transfer end

TCLKA,

TCLKB,

TCLKC,

TCLKD

MTU2 timer clock

input

External clock input pins for the timer

TIOC0A,

TIOC0B,

TIOC0C,

TIOC0D

I/O

MTU2 input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input

capture input/output compare

output/PWM output pins.

TIOC1A,

TIOC1B

I/O

MTU2 input

capture/output

compare

(channel 1)

The TGRA_1 and TGRB_1 input

capture input/output compare

output/PWM output pins.

TIOC2A,

TIOC2B

I/O

MTU2 input

capture/output

compare

(channel 2)

The TGRA_2 and TGRB_2 input

capture input/output compare

output/PWM output pins.

TIOC3A,

TIOC3B,

TIOC3C,

TIOC3D

I/O

MTU2 input

capture/output

compare

(channel 3)

The TGRA_3 to TGRD_3 input

capture input/output compare

output/PWM output pins.

TIOC4A,

TIOC4B,

TIOC4C,

TIOC4D

I/O

MTU2 input

capture/output

compare

(channel 4)

The TGRA_4 and TGRB_4 input

capture input/output compare

output/PWM output pins.

Multi-function

timer pulse unit 2

(MTU2)

TIOC5U,

TIOC5V,

TIOC5W

MTU2 input

capture

(channel 5)

The TGRU_5, TGRV_5, and

TGRW_5 input capture input/dead

time compensation input pins.

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