SH7201 datasheet(15/1196 Pages) RENESAS

15 / 1196 page

Rev. 2.00 Sep. 07, 2007 Page xv of xxviii

Section 11 Direct Memory Access Controller (DMAC) ...................................301

11.1

Features.............................................................................................................................. 301

11.2

Input/Output Pins ...............................................................................................................303

11.3

Register Descriptions ......................................................................................................... 304

11.3.1 DMA Current Source Address Register (DMCSADR) ........................................ 308

11.3.2 DMA Current Destination Address Register (DMCDADR) ................................ 309

11.3.3 DMA Current Byte Count Register (DMCBCT) .................................................. 310

11.3.4 DMA Reload Source Address Register (DMRSADR) ......................................... 311

11.3.5 DMA Reload Destination Address Register (DMRDADR) ................................. 312

11.3.6 DMA Reload Byte Count Register (DMRBCT) ................................................... 313

11.3.7 DMA Mode Register (DMMOD) ......................................................................... 314

11.3.8 DMA Control Register A (DMCNTA) ................................................................. 320

11.3.9 DMA Control Register B (DMCNTB) ................................................................. 328

11.3.10 DMA Activation Control Register (DMSCNT).................................................... 334

11.3.11 DMA Interrupt Control Register (DMICNT) ....................................................... 335

11.3.12 DMA Common Interrupt Control Register (DMICNTA)..................................... 336

11.3.13 DMA Interrupt Status Register (DMISTS) ........................................................... 337

11.3.14 DMA Transfer End Detection Register (DMEDET) ............................................ 338

11.3.15 DMA Arbitration Status Register (DMASTS)...................................................... 340

11.4

Operation ........................................................................................................................... 342

11.4.1 DMA Transfer Mode ............................................................................................ 342

11.4.2 DMA Transfer Condition...................................................................................... 344

11.4.3 DMA Activation ................................................................................................... 348

11.5

Completion of DMA Transfer and Interrupts .................................................................... 349

11.5.1 Completion of DMA Transfer .............................................................................. 349

11.5.2 DMA Interrupt Requests....................................................................................... 350

11.5.3 DMA End Signal Output ...................................................................................... 352

11.6

Suspending, Restarting, and Stopping of DMA Transfer .................................................. 354

11.6.1 Suspending and Restarting DMA Transfer ........................................................... 354

11.6.2 Stopping DMA Transfer on Any Channel ............................................................ 354

11.7

DMA Requests................................................................................................................... 355

11.7.1 Sources of DMA Requests.................................................................................... 355

11.7.2 Synchronous Circuits for DMA Request Signals.................................................. 355

11.7.3 Sense Mode for DMA Requests............................................................................ 356

11.8

Determining DMA Channel Priority.................................................................................. 359

11.8.1 Channel Priority Order.......................................................................................... 359

11.8.2 Operation during Multiple DMA Requests........................................................... 359

11.8.3 Output of the DMA Acknowledge and DNA Active Signals ............................... 360

11.9

Units of Transfer and Positioning of Bytes for Transfer.................................................... 362

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