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SH7201 Datasheet(PDF) 65 Page - Renesas Technology Corp |
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SH7201 Datasheet(HTML) 65 Page - Renesas Technology Corp |
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65 / 1196 page  Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 37 of 1164 REJ09B0321-0200 Instruction Formats Source Operand Destination Operand Example ni format nnnn iiii xxxx 15 0 iiii iiiiiiii: Immediate nnnn: Register direct ADD #imm,Rn nnnn: Register direct iii: Immediate — BLD #imm3,Rn ni3 format xxxx nnnn xxxx 15 0 iii x — nnnn: Register direct iii: Immediate BST #imm3,Rn ni20 format iiii iiii iiii iiii 15 0 xxxx iiii xxxx nnnn 32 16 iiiiiiiiiiiiiiiiiiii: Immediate nnnn: Register direct MOVI20 #imm20, Rn nnnndddddddddddd : Register indirect with displacement iii: Immediate — BLD.B #imm3,@(disp12,Rn) nid format xiii dddd dddd dddd 15 0 xxxx nnnn xxxx xxxx 32 16 — nnnndddddddddddd : Register indirect with displacement iii: Immediate BST.B #imm3,@(disp12,Rn) Note: * In multiply-and-accumulate instructions, nnnn is the source register. |
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