SH7201 datasheet(61/1196 Pages) RENESAS

61 / 1196 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 33 of 1164

REJ09B0321-0200

Addressing Mode

Instruction Format

Effective Address Calculation

Equation

PC relative

disp:12

The effective address is the sum of PC value and

the value that is obtained by doubling the sign-

extended 12-bit displacement (disp).

disp

(sign-extended)

PC + disp

× 2

PC + disp

× 2

The effective address is the sum of PC value and

Rn.

PC + Rn

The 20-bit immediate data (imm) for the MOVI20

instruction is sign-extended.

Sign-

extended

imm (20 bits)

—

Immediate

#imm:20

The 20-bit immediate data (imm) for the MOVI20S

instruction is shifted by eight bits to the left, the

upper bits are sign-extended, and the lower bits

are padded with zero.

Sign-extended

imm (20 bits) 00000000

31 27

—

#imm:8

The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions is zero-extended.

—

#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions is sign-extended.

—

#imm:8

The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.

—

#imm:3

The 3-bit immediate data (imm) for the BAND,

BOR, BXOR, BST, BLD, BSET, and BCLR

instructions indicates the target bit location.

—

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