SH7201 datasheet(50/1196 Pages) RENESAS

50 / 1196 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 22 of 1164

REJ09B0321-0200

(2)

Global Base Register (GBR)

GBR is referenced as the base address in a GBR-referencing MOV instruction.

(3)

Vector Base Register (VBR)

VBR is referenced as the branch destination base address in the event of an exception or an

interrupt.

(4)

Jump Table Base Register (TBR)

TBR is referenced as the start address of a function table located in memory in a

JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.

2.1.3

System Registers

The system registers consist of four 32-bit registers: the high and low multiply and accumulate

registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH

and MACL store the results of multiply or multiply and accumulate operations. PR stores the

return address from a subroutine procedure. PC indicates the program address being executed and

controls the flow of the processing.

MACL

MACH

Multiply and accumulate register high (MACH) and multiply

and accumulate register low (MACL):

Store the results of multiply or multiply and accumulate operations.

Procedure register (PR):

Stores the return address from a subroutine procedure.

Program counter (PC):

Indicates the four bytes ahead of the current instruction.

Figure 2.3 System Registers

(1)

Multiply and Accumulate Register High (MACH) and Multiply and Accumulate

MACH and MACL are used as the addition value in a MAC instruction, and store the result of a

MAC or MUL instruction.

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