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HD64F36022 Datasheet(PDF) 181 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 181 Page - Renesas Technology Corp |
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181 / 384 page ![]() Section 11 Timer W Rev. 4.00 Sep. 23, 2005 Page 155 of 354 REJ09B0025-0400 Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs. TCNT value GRA H'0000 GRD Time GRB H'0200 H'0520 FTIOB H'0200 H'0450 H'0520 H'0450 GRB H'0450 H'0520 H'0200 Figure 11.11 Buffer Operation Example (Output Compare) |
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