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HD64F36022 Datasheet(PDF) 185 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 185 Page - Renesas Technology Corp |
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185 / 384 page ![]() Section 11 Timer W Rev. 4.00 Sep. 23, 2005 Page 159 of 354 REJ09B0025-0400 11.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 11.16 shows the output compare timing. GRA to GRD TCNT TCNT input clock φ N N N+1 Compare match signal FTIOA to FTIOD Figure 11.16 Output Compare Output Timing |
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