HD64F36022 datasheet(189/384 Pages) RENESAS

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Section 11 Timer W

Rev. 4.00 Sep. 23, 2005 Page 163 of 354

REJ09B0025-0400

11.5.8

Timing of Status Flag Clearing

When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag

is cleared. Figure 11.23 shows the status flag clearing timing.

IMFA to IMFD

Write signal

Address

TSRW address

IRRTW

TSRW write cycle

Figure 11.23 Timing of Status Flag Clearing by CPU

11.6

Usage Notes

The following types of contention or operation can occur in timer W operation.

1. The pulse width of the input clock signal and the input capture signal must be at least two

system clock (

φ) cycles; shorter pulses will not be detected correctly.

2. Writing to registers is performed in the T2 state of a TCNT write cycle.

If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter

takes priority and the write is not performed, as shown in figure 11.24. If counting-up is

generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes

precedence.

3. Depending on the timing, TCNT may be incremented by a switch between different internal

clock sources. When TCNT is internally clocked, an increment pulse is generated from the

rising edge of an internal clock signal, that is divided system clock (

φ). Therefore, as shown in

figure 11.25 the switch is from a low clock signal to a high clock signal, the switchover is seen

as a rising edge, causing TCNT to increment.

4. If timer W enters module standby mode while an interrupt request is generated, the interrupt

request cannot be cleared. Before entering module standby mode, disable interrupt requests.

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