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HD64F36022 Datasheet(PDF) 187 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 384 page  Section 11 Timer W Rev. 4.00 Sep. 23, 2005 Page 161 of 354 REJ09B0025-0400 11.5.5 Buffer Operation Timing Figures 11.19 and 11.20 show the buffer operation timing. GRC, GRD Compare match signal TCNT φ GRA, GRB N N+1 M M Figure 11.19 Buffer Operation Timing (Compare Match) GRA, GRB TCNT Input capture signal φ GRC, GRD N M M N+1 N N N+1 Figure 11.20 Buffer Operation Timing (Input Capture) 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. |
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