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HD64F36022 Datasheet(PDF) 195 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 195 Page - Renesas Technology Corp |
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195 / 384 page ![]() Section 12 Watchdog Timer Rev. 4.00 Sep. 23, 2005 Page 169 of 354 REJ09B0025-0400 Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing condition] • Reset by RES pin • When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1 1 B0WI 1 R/W Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1. 0 WRST 0 R/W Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing condition] • Reset by RES pin • When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit=1 12.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. |
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