HD64F36022 datasheet(229/384 Pages) RENESAS

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Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 203 of 354

REJ09B0025-0400

13.5.4

Serial Data Reception (Clocked Synchronous Mode)

Figure 13.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In

serial reception, the SCI3 operates as described below.

The SCI3 performs internal initialization synchronous with a synchronization clock input or

output, starts receiving data.

The SCI3 stores the receive data in RSR.

If an overrun error occurs (when reception of the next data is completed while the RDRF flag

in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this

time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the

RDRF flag remains to be set to 1.

If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is

generated.

Serial

clock

Serial

data

1 frame

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

RDRF

OER

LSI

operation

User

processing

RXI interrupt request generated

RDR data read

RDRF flag

cleared

to 0

RXI interrupt

request

generated

ERI interrupt request

generated by

overrun error

Overrun error

processing

RDR data has

not been read

(RDRF = 1)

Figure 13.12 Example of SCI3 Reception in Clocked Synchronous Mode

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.13 shows a sample flow

chart for serial data reception.

HD64F36022 Datasheet(PDF) 229 Page - Renesas Technology Corp

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