HD64F36022 datasheet(228/384 Pages) RENESAS

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Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 202 of 354

REJ09B0025-0400

Serial

clock

Serial

data

Bit 1

Bit 0

Bit 7

Bit 0

1 frame

Bit 1

Bit 6

Bit 7

TDRE

TEND

LSI

operation

User

processing

TXI interrupt request generated

Data written

to TDR

TDRE flag

cleared

to 0

TXI interrupt

request

generated

TEI interrupt request

generated

Figure 13.10 Example of SCI3 Transmission in Clocked Synchronous Mode

<End>

Yes

Start transmission

Read TDRE flag in SSR

[1]

Write transmit data to TDR

Yes

Read TEND flag in SSR

[2]

Clear TE bit in SCR3 to 0

TDRE = 1

All data transmitted?

TEND = 1

[1]

Read SSR and check that the TDRE flag is

set to 1, then write transmit data to TDR.

When data is written to TDR, the TDRE flag

is automatically cleared to 0 and clocks are

output to start the data transmission.

[2]

To continue serial transmission, be sure to

read 1 from the TDRE flag to confirm that

writing is possible, then write data to TDR.

When data is written to TDR, the TDRE flag

is automatically cleared to 0.

Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)

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