HD64F36022 datasheet(227/384 Pages) RENESAS

227 / 384 page

Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 201 of 354

REJ09B0025-0400

13.5.2

SCI3 Initialization

Before transmitting and receiving data, the SCI3 should be initialized as described in a sample

flowchart in figure 13.4.

13.5.3

Serial Data Transmission

Figure 13.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.

In serial transmission, the SCI3 operates as described below.

1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data

has been written to TDR, and transfers the data from TDR to TSR.

2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at

this time, a transmit data empty interrupt (TXI) is generated.

3. 8-bit data is sent from the TXD pin synchronized with the output clock when output clock

mode has been specified, and synchronized with the input clock when use of an external clock

has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD

pin.

4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains

the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt

request is generated.

The SCK3 pin is fixed high at the end of transmission.

Figure 13.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.

Make sure that the receive error flags are cleared to 0 before starting transmission.

HD64F36022 Datasheet(PDF) 227 Page - Renesas Technology Corp